1. Field of the Invention
The present invention relates to the synchronisation of pipelines in a data processing apparatus, and more particularly to an apparatus and method for synchronising a first pipeline and a second pipeline of a processor arranged to execute a sequence of instructions.
2. Description of the Prior Art
Pipelined processors are used to enable multiple instructions to be in the process of being executed at the same time. Rather than having to wait until the execution of one instruction has fully completed before providing the next instruction to the processor, a pipelined processor is able to receive new instructions into the pipeline whilst other instructions are still in the process of being executed at subsequent pipeline stages of the pipeline, thereby significantly improving the performance.
To further seek to improve the performance of pipelined processors, it is known to provide a processor with multiple pipelines rather than just a single pipeline. As an example, a pipeline may be provided for dealing with load and store instructions, whilst a different pipeline may be provided for dealing with arithmetic instructions. Typically, the first part of each pipeline is unified such that there is a common pipeline for the earlier stages of instruction execution, such as decode and issue stages.
With processors that have multiple pipelines, one problem that can occur is that of synchronisation between the instructions in the multiple pipelines. A final stage in each pipeline typically takes the form of a retirement stage, during which the state of the data processing apparatus is updated dependent on the result of the execution of the instruction that is then in that retirement stage. It will be appreciated that an instruction that has been routed into one of the pipelines may move through that pipeline at a different rate to an instruction that has been routed into a second of the pipelines since, for example, stall cycles may need to be introduced into one of the pipelines to allow one or more instructions in that pipeline to be executed correctly. The result of this is that instructions will not necessary reach the retirement stage of their respective pipelines in their original ordering within the instruction sequence. As an example, if a load instruction is followed by an add instruction in the original instruction sequence, it is possible that the add instruction may reach the retirement stage of its pipeline before the load instruction reaches the retirement stage of its pipeline.
Whilst many data processing apparatus allow out or order retirement of instructions, and hence can accommodate such scenarios, it is however important to know when retiring an instruction that any preceding instruction in the instruction sequence that may not yet have been retired will not give rise to an exception. This is due to the fact that if an earlier instruction were to give rise to an exception, this would typically indicate that the later instructions should not be executed, and accordingly it would be important that none of those later instructions were retired.
One way to deal with this problem is to ensure that the instructions remain within a unified pipeline until a point is reached where the exception status of each instruction has been resolved. Hence, the instructions remain in order until the exception status has been resolved, and only thereafter are allowed to be spilt into multiple pipelines to seek to improve processing performance.
However, it has been found that such an approach limits the performance benefit to be gained from using multiple pipelines, due to the need to wait for the exception status to be resolved before any particular instruction can be routed into one of the multiple pipelines. This results in the resolving of the exception status of each instruction becoming a critical path within the processor, ultimately limiting the speed at which the processor can be run.
Accordingly, it would be desirable to allow instructions to be passed into one of the multiple pipelines before the exception status had been resolved. However, as discussed earlier, this then gives rise to the problem of synchronisation between the pipelines, since even where out of order retirement is allowed, it is still appropriate to determine prior to retiring an instruction that no preceding instructions in the sequence may give rise to an exception.
Accordingly, it is an object of the present invention to provide a technique for synchronisation between multiple pipelines that alleviates the above described problem.